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U63764 obsolete - not recommended for new designs 1 march 31, 2006 stk control #ml0055 rev 1.0 capstore 8k x 8 nvsram pin configuration pin description top view 1 n.c. vcc 28 2 a12 w 27 4 a6 a8 25 5 a5 a9 24 3 a7 n.c. 26 6 a4 a11 23 7 a3 g 22 8 a2 a10 21 12 dq1 dq5 17 9 a1 e 20 10 a0 dq7 19 11 dq0 dq6 18 13 dq2 dq4 16 14 vss dq3 15 pdip signal name signal description a0 - a12 address inputs dq0 - dq7 data in/out e chip enable g output enable w write enable vcc power supply voltage vss ground ? cmos non- volatile static ram 8192 x 8 bits ? 70 ns access time ? 35 ns output enable access time ? i cc = 15 ma at 200 ns cycle time ? unlimited read and write cycles to sram ? automatic store to eeprom on power down using charge stored in an integrated capacitor ? software initiated store ? automatic store timing ? 10 5 store cycles to eeprom ? 10 years data retention in eeprom ? automatic recall on power up ? software recall initiation ? unlimited recall cycles from eeprom ? single 5 v 10 % operation ? operating temperature range: 0 to 70 c -40 to 85 c ? qs 9000 quality standard ? esd protection > 2000 v (mil std 883c m3015.7) ? rohs compliance and pb- free ? package: pdip28 (600 mil) the U63764 has two separate modes of operation: sram mode and nonvolatile mode. in sram mode, the memory operates as an ordinary static ram. in non-volatile operation, data is transferred in parallel from sram to eeprom or from eeprom to sram. in this mode sram functions are disab- led. the U63764 is a static ram with a non-volatile electrically erasable prom (eeprom) element incor- porated in each static memory cell. the sram can be read and written an unlimited number of times, while independent nonvolatile data resi- des in eeprom. data transfers from the sram to the eeprom (the store operation) take place automatically upon power down using charge stored in an integra- ted capacitor. transfers from the eeprom to the sram (the recall operation) take place automatically on power up. the U63764 combines the ease of use of an sram with nonvolatile data integrity. store cycles also may be initia- ted under user control via a soft- ware sequence. once a store cycle is initiated, further input or output are disabled until the cycle is completed. because a sequence of addresses is used for store initiation, it is important that no other read or write accesses intervene in the sequence or the sequence will be aborted. recall cycles may also be initia- ted by a software sequence. internally, recall is a two step procedure. first, the sram data is cleared and second, the nonvola- tile information is transferred into the sram cells. the recall operation in no way alters the data in the eeprom cells. the nonvolatile data can be recalled an unlimited number of times. the U63764 is pin compatible with standard srams and standard bat- tery backed srams. features description
U63764 2 march 31, 2006 stk control #ml0055 rev 1.0 block diagram operating mode e w g dq0 - dq7 standby/not selected h ** high-z internal read l h h high-z read l h l data outputs low-z write l l * data inputs high-z truth table for sram operations a: stresses greater than those listed under ?absolute maximum rati ngs? may cause permanent damage to the device. this is a stre ss rating only, and functional operation of the device at condition a bove those indicated in the operational sections of this spe cification is not implied. exposure to absolute maximum rating c onditions for extended periods may affect reliability. absolute maximum ratings a symbol min. max. unit power supply voltage v cc -0.5 7 v input voltage v i -0.3 v cc +0.5 v output voltage v o -0.3 v cc +0.5 v power dissipation p d 1w operating temperature c-type k-type t a 0 -40 70 85 c c storage temperature t stg -65 150 c characteristics all voltages are referenced to v ss = 0 v (ground). all characteristics are valid in the power supply vo ltage range and in the operating temperature range specified. dynamic measurements are based on a rise and fall time of 5 ns, measured between 10 % and 90 % of v i , as well as input levels of v il = 0 v and v ih = 3 v. the timing reference level of all input and output signals is 1.5 v, with the exception of the t dis -times and t en -times, in which cases transition is measured 200 mv from steady-state voltage. * h or l eeprom array 128x (64 x 8) store recall sram array 128rows x 64 x 8 columns a0 - a12 store/ recall control row decoder v cc v ss g e w software detect power control v cc a5 a6 a7 a8 a9 a11 a12 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 column i/o column decoder a0 a1 a2 a3 a4 a10 input buffers
U63764 3 march 31, 2006 stk control #ml0055 rev 1.0 b: i cc1 and i cc3 are depedent on output loading and cycle rate. the specified values are obtained with outputs unloaded. the current i cc1 is measured for write/read - ratio of 1/2. c: i cc2 is the average current required for the duration of the softstore store cycle. d: bringing e v ih will not produce standby current levels until a software initiated nonvolatile cycle in progress has timed out. see mode selection table. the current i cc(sb)1 is measured for write/read - ratio of 1/2. dc characteristics symbol conditions c-type k-type unit min. max. min. max. operating supply current b i cc1 v cc v il v ih t c = 5.5 v = 0.8 v = 2.2 v = 70 ns 60 65 ma average supply current during c store i cc2 v cc e w v il v ih = 5.5 v 0.2 v v cc -0.2 v 0.2 v v cc -0.2 v 67ma operating supply current b at t cr = 200 ns (cycling cmos input levels) i cc3 v cc w v il v ih = 5.5 v v cc -0.2 v 0.2 v v cc -0.2 v 15 15 ma standby supply current d (cycling ttl input levels) i cc(sb)1 v cc e t c = 5.5 v = v ih = 70 ns 20 22 ma standby supply curent d (stable cmos input levels) i cc(sb) v cc e v il v ih = 5.5 v v cc -0.2 v 0.2 v v cc -0.2 v 33ma recommended operating conditions symbol conditions min. max. unit power supply voltage v cc 4.5 5.5 v input low voltage v il -2 v at pulse width 10 ns permitted -0.3 0.8 v input high voltage v ih 2.2 v cc +0.3 v
U63764 4 march 31, 2006 stk control #ml0055 rev 1.0 dc characteristics symbol conditions c-type k-type unit min. max. min. max. output high voltage output low voltage v oh v ol v cc i oh i ol = 4.5 v =-4 ma = 8 ma 2.4 0.4 2.4 0.4 v v output high current output low current i oh i ol v cc v oh v ol = 4.5 v = 2.4 v = 0.4 v 8 -4 8 -4 ma ma input leakage current high low i ih i il v cc v ih v il = 5.5 v = 5.5 v = 0 v -1 1 -1 1 a a output leakage current high at three-state- output low at three-state- output i ohz i olz v cc v oh v ol = 5.5 v = 5.5 v = 0 v -1 1 -1 1 a a sram memory operations no. switching characteristics read cycle symbol min. max. unit alt. iec 1 read cycle time f t avav t cr 70 ns 2 address access time to data valid g t avqv t a(a) 70 ns 3 chip enable access time to data valid t elqv t a(e) 70 ns 4 output enable access time to data valid t glqv t a(g) 35 ns 5e high to output in high-z h t ehqz t dis(e) 25 ns 6g high to output in high-z h t ghqz t dis(g) 25 ns 7e low to output in low-z t elqx t en(e) 5ns 8g low to output in low-z t glqx t en(g) 0ns 9 output hold time after address change t axqx t v(a) 3ns 10 chip enable to power active e t elicch t pu 0ns 11 chip disable to power standby d, e t ehiccl t pd 70 ns e: parameter guaranteed but not tested. f: device is continuously selected with e and g both low. g: address valid prior to or coincident with e transition low. h: measured 200 mv from steady state output voltage.
U63764 5 march 31, 2006 stk control #ml0055 rev 1.0 read cycle 1: ai-controlled (during read cycle: e = g = v il , w = v ih ) f read cycle 2: g -, e -controlled (during read cycle: w = v ih ) g no. switching characteristics write cycle symbol min. max. unit alt. #1 alt. #2 iec 12 write cycle time t avav t avav t cw 70 ns 13 write pulse width t wlwh t w(w) 55 ns 14 write pulse width setup time t wleh t su(w) 55 ns 15 address setup time t avwl t avel t su(a) 0ns 16 address valid to end of write t avwh t aveh t su(a-wh) 55 ns 17 chip enable setup time t elwh t su(e) 55 ns 18 chip enable to end of write t eleh t w(e) 55 ns 19 data setup time to end of write t dvwh t dveh t su(d) 30 ns 20 data hold time after end of write t whdx t ehdx t h(d) 0ns 21 address hold after end of write t whax t ehax t h(a) 0ns 22 w low to output in high-z h, i t wlqz t dis(w) 25 ns 23 w high to output in low-z t whqx t en(w) 5ns t a(a) previous data valid output data valid t cr address valid t v(a) ai dqi output (1) (2) (9) ai e g t dis(e) t cr t a(e) t en(e) t en(g) t a(g) t dis(g) address valid output data valid i cc active standby t pd t pu (1) (3) (4) (5) (7) (6) (8) (10) (11) t a(a) (2) high impedance dqi output
U63764 6 march 31, 2006 stk control #ml0055 rev 1.0 l- to h-level undefined h- to l-level i: if w is low and when e goes low, the outputs remain in the high impedance state. j: e or w must be v ih during address transition. write cycle #1: w -controlled j t h(d) ai e w dqi input dqi output t cw t su(e) t h(a ) t w(w) t su(d) t dis(w) t en(w) address valid input data valid high impedance t su(a-wh) (12) (16) (13) (19) (20) (23) (21) t su(a) t h(d) ai e w dqi input dqi output t cw t w(e) t h(a) t su(d) address valid input data valid t su(w) (12) (18) (21) (20) (19) previous data high impedance t su(a) write cycle #2: e -controlled j (17) (15) (22) (15) (14)
U63764 7 march 31, 2006 stk control #ml0055 rev 1.0 nonvolatile memory operations mode selection e w a12 - a0 (hex) mode i/o power notes h x x not selected output high z standby l h x read sram output data active m l l x write sram input data active l h 0000 1555 0aaa 1fff 10f0 0f0f read sram read sram read sram read sram read sram nonvolatile store output data output data output data output data output data output high z active k, l k, l k, l k, l k, l k, l l h 0000 1555 0aaa 1fff 10f0 0f0e read sram read sram read sram read sram read sram nonvolatile recall output data output data output data output data output data output high z active k, l k, l k, l k, l k, l k, l k: the six consecutive addresses must be in order listed. w must be high during all six consecutive cycles. see store cycle and recall cycle tables and diagrams for further details. the following six-address sequence is used for testing purposes and should not be used: 0000, 1555, 0aaa, 1fff, 10f0, 139c. l: activation of nonvolatile cycles does not depend on the state of g . m: i/o state assumes that g v il . no. powerstore power up recall symbol conditions min. max. unit alt. iec 24 power up recall duration n t restore 650 s 25 store cycle duration f, e t pdstore 10 ms 26 time allowed to complete sram cycle f t delay 1 s low voltage trigger level v switch 4.0 4.5 v n: t restore starts from the time v cc rises above v switch .
U63764 8 march 31, 2006 stk control #ml0055 rev 1.0 o: the software sequence is clocked with e controlled reads. p: once the software controlled store or recall cycle is initiated, it completes automatically, ignoring all inputs. q: note that store cycles (but not recall) are inhibited by v cc < v switch (store inhibit). r: an automatic recall also takes place at power up, starting when v cc exceeds v switch and takes t restore . v cc must not drop below v switch once it has been exceeded for t he recall to function properly. s: noise on the e pin may trigger multiple read cycles from the same address and abort the address sequence. t: if the chip enable pulse width is less than t a(e) (see read cycle) but greater than or equal t w(e)sr , than the data may not be valid at the end of the low pulse, however the store or recall will still be initiated. no. software controlled store/ recall cycle k, o symbol min. max. unit alt. iec 27 store/recall initiation time t avav t cr 70 ns 28 chip enable to output inactive p t elqz t dis(e)sr 600 ns 29 store cycle time q t elqxs t d(e)s 10 ms 30 recall cycle time r t elqxr t d(e)r 20 s 31 address setup to chip enable s t aveln t su(a)sr 0ns 32 chip enable pulse width s, t t elehn t w(e)sr 60 ns 33 chip disable to address change s t ehaxn t h(a)sr 0ns powerstore and automatic power up recall v cc 5.0 v t powerstore power up v switch w dqi power up recall brown out t restore t restore brown out powerstore (no sram writes) recall (24) (24) no store t pdstore t delay (25)
U63764 9 march 31, 2006 stk control #ml0055 rev 1.0 t cr t su(a)sr t w(e)sr high impedance address 1 valid valid software controlled store/recall cycle t, u, v (e = high after store initiation) address 6 t cr t d(e)s u: w must be high when e is low during the address sequence in order to initiate a nonvolatile cycle. g may be either high or low throughout. addresses 1 through 6 are found in the mode selecti on table. address 6 determines wheter the U63764 performs a stor e or recall. v: e must be used to clock in the address sequence for the software controlled store and recall cycles. t dis(e)sr (28) (27) (27) (33) (32) (31) (29) (30) t h(a)sr t cr t w(e)sr high impedance address 1 valid valid address 6 t d(e)s (31) (32) (29) t h(a)sr (35) (34) t su(a)sr (33) t dis(e)sr (30) t h(a)sr (35) t su(a)sr (33) software controlled store/recall cycle t, u, v (e = low after store initiation) ai e dqi output ai e dqi output t d(e)r t d(e)r
U63764 10 march 31, 2006 stk control #ml0055 rev 1.0 test configuration for functional check w: in measurement of t dis -times and t en -times the capacitance is 5 pf. x: between v cc and v ss must be connected a high frequency bypass capacitor 0.1 f to avoid disturbances. capacitance e conditions symbol min. max. unit input capacitance v cc v i f t a = 5.0 v = v ss = 1 mhz = 25 c c i 8pf output capacitance c o 7pf all pins not under test must be connected with ground by capacitors. v ih v il v ss 480 255 30 pf w v o simultaneous measure- ment of all 8 output pins input level according to the relevant test measurement dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 e w g 5 v v cc x operating temperature range c = 0 to 70 c k = -40 to 85 c g1 d 70 k U63764 type package d = pdip28 (600mil) ordering code leadfree option blank = standard package g1 = leadfree green package y access time 70 = 70 ns y: on special request example date of manufacture (the first 2 digits indicating the year, and the last 2 digits the calendar week.) leadfree green package product specification internal code device marking (example) zmd U63764dk 70 z 0425 g1
U63764 11 march 31, 2006 stk control #ml0055 rev 1.0 device operation the U63764 has two separate modes of operation: sram mode and nonvolatile mode. the memory ope- rates in sram mode as a standard static ram. data is transferred in nonvolatile mode from sram to eeprom (the store operation) or from eeprom to sram (the recall operation). in this mode sram functions are disabled. store cycles may be initiated under user control via a software sequence and are also automatically initiated when the power supply voltage level of the chip falls below v switch . recall operations are automatically initiated upon power up and may also occur when the v cc rises above v switch , after a low power condition. recall cycles may also be initiated by a software sequence. sram read the U63764 performs a read cycle whenever e and g are low and w is high. the address specified on pins a0 - a12 determines which of the 8192 data bytes will be accessed. when the read is initiated by an address transition, the outputs will be valid after a delay of t cr . if the read is initiated by e or g , the outputs will be valid at t a(e) or at t a(g) , whichever is later. the data outputs will repeatedly respond to address changes within the t cr access time without the need for transition on any control input pins, and will remain valid until another address change or until e or g is brought high or w is brought low. sram write a write cycle is performed whenever e and w are low. the address inputs must be stable prior to entering the write cycle and must remain stable until either e or w goes high at the end of the cycle. the data on pins dq0 - 7 will be written into the memory if it is valid t su(d) before the end of a w controlled write or t su(d) before the end of an e controlled write. it is recommended that g is kept high during the entire write cycle to avoid data bus contention on the common i/o lines. if g is left low, internal circuitry will turn off the output buffers t dis (w) after w goes low. automatic store during normal operation, the U63764 will draw current from v cc to charge up an integrated capacitor. this stored charge will be used by the chip to perform a sin- gle store operation. if the voltage on the v cc pin drops below v switch , the part will automatically discon- nect the internal components from the external power supply with a typical delay of 150 ns and initiate a store operation with t pdstore max. 10 ms. in order to prevent unneeded store operations, auto- matic store will be ignored unless at least one write operation has taken place since the most recent store or recall cycle. software initiated store cycles are performed regardless of whether or not a write operation has taken place. sram read and write operations that are in pro- gress after an automatic store cycle on power down is requested are given time to complete before the store operation is initiated. during t delay multiple sram read operations may take place. if a write is in progress it will be allowed a time, t delay , to complete. any sram write cycles requested after the v cc pin drops below v switch will be inhibited. automatic recall during power up, an automatic recall takes place. at a low power condition (power supply voltage < v switch ) an internal recall request may be latched. as soon as power supply voltage exceeds the sense voltage of v switch , a requested recall cycle will automatically be initiated and will take t restore to complete. if the U63764 is in a write state at the end of power up recall, the sram data will be corrupted. to help avoid this situation, a 10 k resistor should be connected between w and power supply voltage. software nonvolatile store the U63764 software controlled store cycle is initia- ted by executing sequential read cycles from six spe- cific address locations. by relying on read cycles only, the U63764 implements nonvolatile operation while remaining compatible with standard 8k x 8 srams. during the store cycle, an erase of the previous non- volatile data is performed first, followed by a parallel programming of all the nonvolatile elements. once a store cycle is initiated, further inputs and outputs are disabled until the cycle is completed. because a sequence of addresses is used for store initiation, it is important that no other read or write accesses intervene in the sequence or the sequence will be aborted. to initiate the store cycle the following read sequence must be performed: 1. read addresses 0000 (hex) valid read 2. read addresses 1555 (hex) valid read 3. read addresses 0aaa (hex) valid read 4. read addresses 1fff (hex) valid read 5. read addresses 10f0 (hex) valid read 6. read addresses 0f0f (hex) initiate store cycle
U63764 12 march 31, 2006 stk control #ml0055 rev 1.0 once the sixth address in the sequence has been entered, the store cycle will commence and the chip will be disabled. it is important that read cycles and not write cycles be used in the sequence, although it is not necessary that g be low for the sequence to be valid. after the t store cycle time has been fulfilled, the sram will again be activated for read and write operation. when v cc < v switch all software store operations will be inhibited. any sram write cycles requested after the v cc pin drops below v switch will be inhibited. software nonvolatile recall a recall cycle of the eeprom data into the sram is initiated with a sequence of read operations in a manner similar to the store initiation. to initiate the recall cycle the following sequence of read opera- tions must be performed: 1. read addresses 0000 (hex) valid read 2. read addresses 1555 (hex) valid read 3. read addresses 0aaa (hex) valid read 4. read addresses 1fff (hex) valid read 5. read addresses 10f0 (hex) valid read 6. read addresses 0f0e (hex) initiate recall cycle internally, recall is a two step procedure. first, the sram data is cleared and second, the nonvolatile information is transferred into the sram cells. after t d(e)r cycle time the sram will once again be ready for read and write operations.the recall operation in no way alters the data in the eeprom cells. the nonvolatile data can be recalled an unlimited number of times. low average active power when e is high the chip consumes only standby cur- rent. the overall average current drawn by the part depends on the following items: 1. cmos or ttl input levels 2. the time during which the chip is disabled (e high) 3. the cycle time for accesses (e low) 4. the ratio of reads to writes 5. the operating temperature 6. the v cc level
march 31, 2006 U63764 life support policy simtek products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the simtek product could create a situation where personal injury or death may occur. components used in life-support devices or systems must be expressly authorized by simtek for such purpose. limited warranty the information in this document has been carefully checked and is believed to be reliable. however, simtek makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it. the information in this document describes the type of component and shall not be considered as assured characteristics. simtek does not guarantee that the use of any information contained herein will not infringe upon the patent, trade- mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. this docu- ment does not in any way extent simtek?s warranty on any product beyond that set forth in its standard terms and conditions of sale. simtek reserves terms of delivery and reserves the right to make changes in the products or specifications, or both, presented in this publication at any time and without notice.
change record date/rev name change 01.11.2001 ivonne steffens format revision and release for ?memory cd 2002? 13.04.2004 matthias schniebel removing ?preliminary? 21.04.2004 matthias schniebel adding ?leadfree green package? to ordering information adding ?device marking? 7.4.2005 stefan gnther page1: add rohs compliance and pb- free 31.3.2006 troy meester changed to obsolete status 1.0 simtek assigned simtek document control number

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